﻿/*
 * Copyright (c) 2023 HiSilicon (Shanghai) Technologies CO., LIMITED.
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef __USB2_CRG_CFG_RB_REG_OFFSET_H__
#define __USB2_CRG_CFG_RB_REG_OFFSET_H__

/* USB2_CRG_CFG_RB Base address of Module's Register */
#define USB2_CRG_CFG_RB_BASE (0x4000a000)

/* **************************************************************************** */
/*                      HH503 USB2_CRG_CFG_RB Registers' Definitions                            */
/* **************************************************************************** */

#define USB2_CRG_CFG_RB_USB2_CTRL_CRG_CFG_REG \
    (USB2_CRG_CFG_RB_BASE + 0x800) /* USB2 CTRL时钟及软复位控制寄存器。 */
#define USB2_CRG_CFG_RB_USB2_PHY_CRG_CFG0_REG \
    (USB2_CRG_CFG_RB_BASE + 0x804) /* USB2 PHY 时钟及软复位控制寄存器。 */
#define USB2_CRG_CFG_RB_USB2_CRG_CFG0_REG \
    (USB2_CRG_CFG_RB_BASE + 0x808) /* USB2 PHY 时钟及软复位控制寄存器。 */
#define USB2_CRG_CFG_RB_USB2_CRG_DIV_CFG_REG \
    (USB2_CRG_CFG_RB_BASE + 0x80C) /* USB2 PHY PCLK分频配置 */

#endif // __USB2_CRG_CFG_RB_REG_OFFSET_H__
